As the demand for greater speed and higher density integrated circuits has increased, there has of course been continued progress towards smaller feature sizes. These smaller features demand improved process technologies so as to maintain the integrity of the circuits in considerably smaller spaces. As an example, a typical back end process flow requires patterning of metal lines and vias down to 0.35 .mu.m and below. The requirement of these smaller features has prompted the growth of a number of key technologies such, for instance, as high density plasma chemical vapor deposition (HDPCVD) for superior gap performance; chemical mechanical polishing (CMP) so as to minimize topography; and new etch chemistries for enhanced selectivities. More particularly, the shrinking of interconnect features in integrated circuits has itself created numerous challenges, including increased resistances of the vias themselves; incidents of vias falling off metal due to poor alignment control; and, significant from a process standpoint, step coverage issues in filling higher aspect ratio vias.
Various techniques to improve such step coverage of barrier metal on vias has been recommended, some are currently in practice; for instance, collimated sputtering, ionized metal plasma (IMP) sputtering and chemical vapor deposition (CVD), as set forth in various articles such as "Metal Ion Deposition From Ionized Magnatron Sputtering Discharge", by S. M. Rossnagel et al., published in J. Vac. Sci. Technol., January/February, 1994 at page 449; "A Robust, Versatile MOCVD TiN Process", by G. A. Dixit et al., 1995, VMIC Conference at page 175; and "Step Coverage Comparison of Ti/TiN Deposited By Collimated and Uncollimated Physical Vapor Deposition Techniques", by Shi-Qing Wang et al., J. Vac. Sci. Technol., May/June, 1996. In addition, aluminum reflow at high temperatures and a dual-damascene process using Cu CVD have been suggested as possible alternatives useful in sub 0.25 .mu.m interconnect technologies and beyond. Even so, device reliability and or manufacturability remain issues of prime concern.
In a conventional 0.35 .mu.m back in flow, metal line structures are patterned from blanket film stacks, followed by deposition of the intermetal dielectric (IMD). After IMD planerization by chemical mechanical polishing (CMP), vias are etched through the dielectric, typically an oxide, through to the metal below. Vias are then filled by depositing a glue or a glue layer consisting of Ti/TiN prior to the CVD tungsten. Subsequent etchback or chemical metal polishing processes complete the via field sequence.